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= = = DUO CAPITOL DESCRIPTION = = =
Architecture by Jack Eisenmann

The DUO Capitol is an 8 bit processor encapsulated within a single chip. The microprocessor has an 8 bit bidirectional data bus and a 16 bit address bus. This allows the chip to access 64 kilobytes of mapped memory.

The CPU is distinguished by its large number of registers, small instruction set, and robust machine code syntax. A variety of applications are suitable for the DUO Capitol, ranging from digital signal processing, to personal computing, to robotics.

= REGISTERS AND STACK =

The processor supports up to 255 general purpose 8 bit registers. Each register is addressed with a single byte.

The 256th register is the over/underflow flag. This special register is modified by certain instructions. When the result of an operation wraps around 0 or 255, the ALU sets the flag register to 1; otherwise, the ALU sets the flag to 0.

The CPU also features a stack of 16 bit words. This stack is used to store and recall the return addresses of function invocations.

= INSTRUCTION SYNTAX =

The DUO Capitol interprets instructions in sequence. Each instruction begins with 4 bits determining the operation (opcode) and 4 bits determining argument types. Several argument bytes may follow.

[opcode] [arg types] [arg?] [arg?]...

For convenience of explanation, we will assign a label to each argument type bit:

[A] [B] [C] [D]

If A is 0, the first argument is a single byte address to a register. If A is 1, the first argument is a two byte address to memory. The value in the specified location will be used by certain instructions.

The bits B and C together specify the type of the second argument. Allow BC to denote the two bit number whose value is B + C*2. If BC is 0, the second argument is a single byte address to a register. If BC is 1, the second argument is a two byte address to memory. When BC is 2, the second argument is a single byte literal. If BC is 3, the second argument will be a two byte literal (IE: a word).

Bit D works in a similar fashion to bit A. If D is 0, the third argument is a single byte address to a register. When D is 1, the third argument is a two byte address to memory.

= LIST OF OPERATIONS =

0000: COP [dest] [data] – Copy data to destination.

1000: ADV [dest] [num] – Advance word at destination by given offset.

0100: NOT [dest] [data?] – Invert data.

1100: AND [dest] [data?] [data] – Bitwise AND.

0010: INC [dest] [num?] – Increment the given number.

1010: DEC [dest] [num?] – Decrement.

0110: ADD [dest] [num?] [num] – Add two numbers.

1110: SUB [dest] [num?] [num] – Subtract.

0001: JPZ [data] [addr] [addr] – Jump to address if data is zero.

1001: JNZ [data] [addr] [addr] – Jump if not zero.

0101: JMP [addr] [addr] – Unconditional jump.

1101: LET [data] [addr] [addr] – Write data to address. (First argument is passed as byte literal.)

0011: SET [data] [addr] [addr] – Write data to address. (First argument is data source address.)

1011: GET [dest] [addr] [addr] – Read data at address.

0111: PSH [addr] [addr] – Push current instruction address onto stack and jump to given address.

1111: POP – Pop word from stack and jump to that address.

= MACHINE CODE SUBTLETIES =

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