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Note: You may want to view the schematics while reading this page.

The DUO uses a 2 kilobyte EEPROM chip to store all the commands for its programs. The data output size for this chip is 8 bits, but the computer uses just 5 bits out of the 8 at a time. This is because all opcodes and arguments are 5 bits wide. 5 bits comprise a "nyckle". Each program may contain 256 nyckles, since program addresses can only contain 8 bits. The extra 3 available address bits are used by the human operator to access and execute different programs in the EEPROM; thus the computer may store up to 8 programs each 256 nyckle long.

A pair of synchronized counter chips determine the current address of execution in the program. Each counter stores 4 bits. The outputs of these chips are attached to an 8 bit buffer, which in turn is attached to the EEPROM address inputs.

Most of the switches on the front panel are used to interface with the EEPROM. One switch toggles output enable mode for the EEPROM, which switches the chip between reading and writing. During programming, output enable is deactivated. When inspecting addresses or running a program, output enable is activated. A set of 5 switches is used to input data (a single nyckle) into the EEPROM. After the correct data has been toggles, the human operator presses the write enable button to write the data in the EEPROM. To modify the current address of the EEPROM, the human operator toggles the manual address switch, which turns the output enable mode off for the EEPROM address buffer, hence preventing the counters from feeding it an address. The operator then toggles a set of 8 address switches, each of which is attached directly to the address of the EEPROM.

The DUO Elite's clock begins with a 555 timer chip which sends a constant on-off clock pulse. The chip may be turned off and on by a switch toggles by the operator. The 555 chip's speed may be changed by toggling another switch, which adds or removes resistance from the chip. The output of this chip is attached to the clock pulse input of a decade counter, which cycles through one of four outputs, causing each one to enter a high state in sequence. The first output of the decade counter is attached to the increment input of a 4 bit counter. This counter determines the current clock step being evaluated. To split the output of this chip into its individual steps, the output of the counter is attached to the address of a 1 bit to 8 bit demultiplexer (demux). The outputs of the demux are used to activate the various timed operations of the computer.

A 4 bit opcode register and 3 4 bit argument registers are used to store the current command so it may be executed. In addition, a 1 bit register stores the conditional prefix bit of the opcode. To load a command into its appropriate registers, the clock first sends a signal to write the EEPROM output to the opcode register and conditional bit register. Next, the EEPROM address counter is incremented. At the same time, the computer determines how many arguments the command will contain based on its opcode. This number of arguments is stored in the arguments remaining counter.

The clock then enters a loop to load the arguments from the EEPROM. During the first step, data is written into one of the argument registers from either the EEPROM or RAM (to be described later). The source data is determined by the prefix bit of the EEPROM by means of a 2 nybble to 1 nybble mux (a nybble is 4 bits). The argument register write signal is sent by a 1 bit to 4 bit demux whose address is determined by the arguments remaining counter. After the appropriate data has been written to the appropriate argument register, the next clock step decrements the arguments remaining counter and increments the EEPROM address counter. If the arguments remaining counter is found to be below 0, then the loop does not repeat. Otherwise, the cycle continues and the next argument is loaded into the next argument register.

The RAM contains 16 nybbles. These nybbles may be modified by commands in the program. The address of the RAM is determined by a 2 nybble to 1 nybble mux, whose source may be either the output of last argument register or the output of EEPROM depending on the clock step. As described earlier, data from the RAM may be called into one of the argument registers through the usage of a prefix bit in the program.

When the command has been completely loaded into the registers, the command is executed with a single clock signal. The arguments of the command are fed into the ALU which contains chips for adding, comparing, and performing bitwise operations. The output of the ALU is then fed into an arrangement of three 2 nybble to 1 nybble muxes. The opcode register is processed by a set of gates to decide which of the 6 nybbles should be fed into the RAM by the muxes. A buffer sits between this set of muxes and the RAM to prevent any interference during other clock steps. Certain argument register outputs and ALU outputs are attached to the EEPROM address counters, the VRAM, and the boolean bit register to perform other commands which modify memory other than the RAM.

The boolean bit register stores a single bit which may be used in conjunction with the conditional bit register to inhibit a command. The input of this bit register is a set of logic gates whose input in turn is the magnitude comparison chip. The logic gates here are used to decide which operation to feed the bit register based on the current opcode.

The VRAM is part of the GPU which displays graphics on the 8 by 8 LED matrix. It consists of the 64 bit VRAM chip, a 2 nybble to 1 nybble mux to determine the VRAM's address, a buffer for the data lines of the VRAM, a counter to determine the current line to display, and a 1 bit to 8 bit demux to sink the appropriate row of the display based on the counter's output.

To provide a write signal to the correct location in the computer, a 1 bit to 16 bit demux is used in combination with a set of logic gates. The operation of these gates is influenced by the boolean and conditional bit registers; depending on their state, the write signal may or may not be inhibited. The timing of the logic gates is controlled by the third output of the decade counter in the processor clock.

The clock steps are summarized here:
1. Write EEPROM data to opcode register
2. Increment EEPROM address counter; set value of arguments remaining register
3. Write EEPROM data to one of the argument registers
4. Increment EEPROM address counter; decrement arguments remaining register
5. Loop back to step 3 if the arguments remaining register is below 0
6. Send a write signal to a specific location in the computer to execute the command

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